A packaged semiconductor device (integrated circuit) typically includes a semiconductor die connected in some manner to inner ends of conductive lines. The outer ends of the conductive lines interface with signals entering and exiting the semiconductor device, from external systems. The packaged semiconductor device may be mounted in a socket or to a printed wiring board (PWB), which board has wiring traces on one or both sides and which may have additional components mounted thereto.
The conductive lines in the semiconductor package include either conductive leads of leadframes, or conductive traces on a substrate, such as a ceramic or printed circuit board (PCB) substrate.
The conductive leads may be relatively flexible, such as for tape automated bonding (TAB), in which case the leads are supported by a tape backing. External, more rigid leads may be connected to the ends of the relatively flexible conductive leads.
On the other hand, the conductive leads of the leadframes may be relatively rigid, such as for plastic molding a package body around the die. In this case, the die is typically mounted to a central die paddle of the lead frame, which may be in-plane or out-of-plane with respect to the conductive leads, and is typically wire bonded to the inner ends of the conductive leads. Outer ends of the conductive leads exit the package. The external (to the package body) portions of the conductive leads may be relatively straight (generally in-plane with respect to the lead frame), or may be bent one or more times to form legs or the like. In either case, the external portions of the leads are typically soldered to wiring traces on a PWB, by surface mounting the package to the PWB, or the leads urge against contacts in a socket.
Modern semiconductor devices may have many leads (high lead count), in which case the external portions of the device leads are small (fine) and of fine pitch (closely-spaced). Avoiding damage to the device leads during handling and assembly to a PWB is a problem addressed by commonly-owned U.S. Pat. No. 5,051,813.
For soldering the leads of the semiconductor device to a PWB, the PWB will have a corresponding large number of closely-spaced wiring traces distributed and spaced to match the pattern of the device leads. Hence, another problem with high lead count devices is that for surface mounting the semiconductor device to the PWB, a high degree of precision and accuracy is required to ensure that the device leads align with the corresponding PWB traces. The aforementioned U.S. Pat. No. 5,051,813 discloses forming plastic webs between the external leads, forming plastic bumps on the webs, and providing the PWB with recesses corresponding to the bumps. The recesses and bumps allow for precise alignment of the device to the PWB, but suffer from what could be perceived as two limitations: (1) a special mold is required to form the bumps; and (2) the bumps and PWB recesses, residing as they do between respective leads and wires, utilize space between the leads and traces and limit the lead/trace pitch that would otherwise be available.
In the main, hereinbelow, plastic packaged semiconductor devices having external leads are discussed, but the techniques disclosed herein have applicability to other types of semiconductor packaging.
Present plastic packaging techniques involve molding a plastic "body" around a semiconductor die. Prior to molding, the die is mounted and connected to a lead frame having a plurality of leads ultimately exiting the package for connecting the semiconductor device to external circuits, such as wiring traces on a printed wiring board (PWB). Various forms of plastic packages are known, including DIP (Dual In-line Package), PQFP (Plastic Quad Flat Pack) and PLCC (plastic leaded chip carrier).